module shift_1x32 (clk, 
		  	shift,
			sr_in,
			sr_out_1,
			sr_out_2
		   );
  
	input clk, shift;
	input sr_in;
	output sr_out_2;
	output sr_out_1;

	reg [31:0] sr;

	always@(posedge clk)
	begin
		if (shift == 1'b1)
		begin
			sr[31:1] <= sr[30:0];
			sr[0] <= sr_in;
		end
	end
	
	assign sr_out_2 = sr[1];
	assign sr_out_1 = sr[0];
endmodule